Clocked logic circuitry such as sequential circuits, state machines, data paths, counters, arithmetic logic units, processors, or the like use a clock signal to advance the circuitry from state to state. The current state of a clocked logic circuit is a function of its previous state, the previous state of other circuitry, or both. Circuit state may be advanced responsive to the rising edge of a clock signal, falling edge, or both. The input to clocked logic circuitry does not affect the present logic state when the clock signal is inactive (i.e., not rising and/or falling). Circuit operation should be completed within a fixed interval of time between two clock pulses, called a ‘clock cycle’, to ensure reliable operation of clocked logic circuitry. Otherwise, circuit behavior becomes unpredictable and may result in failure.
Performance of clocked logic circuitry is limited by the amount of time needed to process previous state information to produce next state information. Conventionally, previous state information is captured during a first portion of a clock cycle and processed during a second portion of the clock cycle to determine the next logic state. Combinatorial logic included in clocked logic circuitry has one or more critical paths that limit circuit performance. Critical paths are circuit paths that limit how fast a circuit operates, e.g., paths that take the most time to generate an output responsive to an input. In clocked logic circuits, critical paths yield state information the determination of which limits circuit performance. Unpredictable circuit behavior (and possibly failure) occurs when state information is not fully determined within a clock cycle. Accordingly, clock cycle duration is conventionally based on the amount of time needed by critical paths to generate state information before advancing clocked logic circuitry to a next state. Clocked logic circuit performance may be improved by generating performance-limiting state information earlier in a clock cycle.